HD6417751RBP240

HD6417751RBP240 Description

The Renesas Electronics America SH-4 microprocessor family has built-in peripheral functions for a wide range of multimedia devices. HD6417751RBP240 is one of the devices in this family that offers stable performance over a supply voltage range of 1.4V to 1.6V. This Microcontroller has a memory size of 48K x 8.

HD6417751RBP240 Features

LSI

• Operating frequency: 240 MHz1/200 MHz1/167 MHz2/133 MHz2
• Performance:
-430 MIPS (240 MHz), 360 MIPS (200 MHz)
-300 MIPS (167 MHz), 240 MIPS (133 MHz)
-1.2 GFLOPS (167 MHz), 0.93 GFLOPS (133 MHz)
-1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz)
• Superscalar architecture: Parallel execution of two instructions
• Packages: 256-pin QFP, 256-pin BGA
• External buses (SH buses)
-Separate 26-bit address and 32-bit data buses
-External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency
• External bus (PCI bus):
-32-bit address/data multiplexing
-Selection of internal clock or external PCI-dedicated clock
CPU
• Original Hitachi SuperH architecture
• 32-bit internal data bus
• General register file:
- Sixteen 32-bit general registers (and eight 32-bit shadow registers)
- Seven 32-bit control registers
- Four 32-bit system registers
• RISC-type instruction set (upward-compatible with SuperH Series)
- Fixed 16-bit instruction length for improved code efficiency
- Load-store architecture
- Delayed branch instructions
- Conditional execution
- C-based instruction set
• Superscalar architecture (providing simultaneous execution of two instructions) including FPU
• Instruction execution time: Maximum 2 instructions/cycle
• Virtual address space: 4 Gbytes (448-Mbyte external memory space)
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• On-chip multiplier
• Five-stage pipeline
FPU
• On-chip floating-point coprocessor
• Supports single-precision (32 bits) and double-precision (64 bits)
• Supports IEEE754-compliant data types and exceptions
• Two rounding modes: Round to Nearest and Round to Zero
• Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754
• Floating-point registers: 32 bits × 16 words × 2 banks (single-precision × 16 words or double-precision × 8 words) × 2 banks
• 32-bit CPU-FPU floating-point communication register (FPUL)
• Supports FMAC (multiply-and-accumulate) instruction
• Supports FDIV (divide) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution times
- Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision)
- Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles (double- precision)
Note: FMAC is supported for single-precision only.
• 3-D graphics instructions (single-precision only):
- 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 7 cycles (latency)
- 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency)
• Five-stage pipeline

HD6417751RBP240 Applications

· Home Devices
· Industrial Applications
· Cell phones
· VCR