MB91194LGA-G-118-ER

■ DESCRIPTION

The MB91191/192 series is a single-chip microcontroller using a 32-bit RISC- CPU (FR series) as its core. It contains peripheral I/O resources suitable for software servo control in applications such as VTRs that require high-speed CPU processing.

■ FEATURES

CPU
• 32-bit RISC (FR series) , load/store architecture, 5-stage pipeline
• General-purpose registers : 16 × 32-bit
• 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle
• Includes memory-to-memory transfer, bit manipulation, and barrel shift instructions : Optimized for embedded applications
• Includes function entry/exit instructions and multiple-register load/store instructions : Instruction set supports high level languages
• Register interlock function : For efficient assembly language coding
• Branch instructions with delay slots : Reduced overhead for branch operations
• Internal multiplier unit is supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupts (PC and PS saving) : 6 cycles, 16 priority levels

Bus Interface

• 16-bit address output, 8/16-bit data input and output
• Basic bus cycle : 2 clock cycles
• Supports interfaces for various types of memory
• Multiplexed data/address input/output
• Automatic wait cycles : Between 0 and 7 wait cycles can be specified independently for each memory area
• Unused data/address pins can be configured as input/output ports
• Supports little endian mode

Bit Search Module

• Searches, starting from the MSB, for the position of the first 1/0 bit transition in a word. The operation is performed in one cycle.

Serial I/O

• 3 channels with internal buffer RAM (automatic transfer of up to 128 bytes)
• Independent send and receive buffer mode (automatic transfer of up to 64 bytes)

A/D Converter (Successive Approximation Type)

• 10-bit × 16 channels
• Uses successive approximation conversion method (conversion time : 8.4 µs @ 20 MHz)
• Channel scan function
• Hardware and software conversion start functions
• Internal FIFO (Software conversion : 6 stages, Hardware conversion : 6 stages)

Timers

• 16-bit × 4 channels
• 16-bit timer/counter × 1 channel (with square wave output)
• 8/16-bit timer/counter × 1 channel (with square wave output)

FG input unit

• Incorporates capstan, drum, and reel input circuits

Capture unit

• Internal 24-bit free-run counter (Minimum resolution = 50 ns @ 20 MHz)
• Internal FIFO (Data : 21-bit × 8, Detection : 8-bit × 8)

Programmable pattern generator

• Internal RAM buffer (PPG0 : 256 bytes, PPG1 : 64 bytes)
• Output timing resolution : 800 ns @ 20 MHz
• Includes an A/D converter hardware start function

Realtime timing generator

• RTG : 3 circuits
• Output timing resolution : 400 ns or 800 ns selectable
• Timing output ports : 5 ports

PWM

• 12-bit PWM × 6 channels (rate, multi-type)
• Base frequency = 78.1 kHz or 39.0 kHz (@ 20 MHz) selectable
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