MB91233LLGA-G-118-ERE1

■ DESCRIPTION

The MB91230 series is a line of standard microcontrollers, based on a 32-bit high-performance RISC CPU and containing variety of I/O resources, for embedded control applications which require high CPU performance at high speed processing.
Audio motor control storage : Designed to specifications for embedded control applications which high CPU performance power processing.
The MB91230 series belongs to the FR60Lite family.

■ FEATURES

• 32-bit RISC, load/store architecture with a 5 stage pipeline
• Maximum operating frequency: 33.6 MHz
(oscillation frequency = 4.2 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method) )
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
• Memory-to-memory transfer, bit handling, and barrel shift instructions, etc.
: Instructions suitable for embedded applications
• Function entry/exit instructions, multiple-register load/store instructions
: Instructions adapted for C-language
• Register interlock function : Facilitates coding in assembler
• Built-in multiplier with instruction-level support
- 32-bit multiplication with sign : 5 cycles
- 16-bit multiplication with sign : 3 cycles
• Interrupt (PC and PS save) : 6 cycles (16 priority levels)
• Harvard architecture allowing program access
and data access to be executed simultaneously
• Instruction compatible with FR family
• Capacity of built-in ROM and ROM type
- MASK ROM : 256 KB
- FLASH ROM : 256 KB
• Capacity of built-in RAM : 16 KB
• General-purpose ports : Maximum 98 ports
(including N-ch open-drain port : 4 ports)
• A/D converter (series-parallel type)
- Resolution : 10-bit : 8 ch (4 ch × 2 unit)
- Conversion time : 1.69 µs (Minimum conversion time)
• D/A converter (R-2R type)
- Resolution : 8-bit : 2 ch (independence)
- Conversion speed : 0.6 µs (when load capacitance 20 pF)
• External interrupt input : 16 ch
• Bit search module (for REALOS)
- Function for searching the MSB (Upper bit) in each word
for the first “0” or “1” inverted point
• UART (full-duplex double buffer) : 4 ch
- Selectable parity On/Off
- Asynchronous (start-stop synchronized) or
clock-synchronous communications selectable
- Internal timer for dedicated baud rate (U-timer) on each channel
- External clock can be used as transfer clock
- Error detection function for parity, frame and overrun
• PPG : 16-bit × 6 ch
• Up/down counter : 2 ch (8-bit × 2 ch or 16-bit × 1 ch)
• Reload timer : 16-bit × 4 ch
• Free-run timer : 16-bit × 2 ch
• Watch timer : 15-bit × 1 ch
• PWC : 8-bit × 2 ch
• Input capture : 2 ch (interface with free-run timer 0)
• Output compare : 4 ch
(free-run timer 0 and output compare unit 0/1 cooperate, free-run timer 1 and
output compare units 2/3)
• LCD controller : SEG00 to SEG31/COM0 to COM3 (also serving as a port)
• Clock monitor (peripheral clock output function) : 1 ch
• Timebase/watchdog timer (26-bit)
• Real-time clock (counting even with the real-time clock stopped)
• Low Power Consumption Mode
• Sleep/stop function
• Package : LQFP-120, FLGA-128
• Technology : CMOS 0.35 µm
• Power supply
• Dual power supply configuration
[internal logic 3.3 V, I/O 5.5 V(3.3 V for ADC and DAC input/output)]