XC5VFX200T-1FFG1738I

Description

Using the second generation ASMBL™ (Advanced Silicon Modular Block) column- based architecture, the Virtex-5 family contains five distinct platforms (sub- families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high- speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability.

Features

High-Performance DSP56300 Core
● 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and 3.3 V I/O
● Object code compatible with the DSP56000 core
● Highly parallel instruction set
● Data arithmetic logic unit (ALU)
- Fully pipelined 24 x 24-bit parallel multiplier-accumulator
- 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)
- Conditional ALU instructions
- 24-bit or 16-bit arithmetic support under software control
● Program control unit (PCU)
- Position independent code (PIC) support
- Addressing modes optimized for DSP applications (including immediate offsets)
- On-chip instruction cache controller
- On-chip memory-expandable hardware stack
- Nested hardware DO loops
- Fast auto-return interrupts
● Direct memory access (DMA)
- Six DMA channels supporting internal and external accesses
- One-, two-, and three- dimensional transfers (including circular buffering)
- End-of-block-transfer interrupts
- Triggering from interrupt lines and all peripherals
● Phase-locked loop (PLL)
- Allows change of low power divide factor (DF) without loss of lock
- Output clock with skew elimination
● Hardware debugging support
- On-Chip Emulation (OnCE) module
- Joint test action group (JTAG) test access port (TAP)
- Address trace mode reflects internal Program RAM accesses at the external port