PSB7238-SFV1.1

Overview

The PSB 7238 Joint Audio Decoder Encoder Multimode (JADE MM) is a device which implements voice compression algorithms using the Low-Delay Code Excited Linear Prediction (LD-CELP) standard as defined in the ITU-T G.728 Recommendation, the Algebraic Code Excited Linear Prediction (ACELP) and the Multi-Pulse Maximum Likelihood Quantization (MP-MLQ) standard as defined in the ITU-T G.723 Recommendation, and for 7-kHz voice using the Sub-Band Coded Adaptive Differential PCM (SBC-ADPCM) coding according to the G.722 Recommendation. In addition G.711 PCM audio coding is also supported.

Feature List

Functions
– G.728 compression/decompression (16 Kbit/s)
– G.723 compression/decompression (6.3, 5.3 Kbit/s)
– G.722 compression/decompression for 7-kHz audio (64, 56, 48 Kbit/s)
– G.711 compression/decompression (64 Kbit/s)
– Outband controlled audio protocol with optimized data rate
– Digital sampling rate conversion (16 kHz - 8 kHz) for G.722 audio with 8-kHz Codec (bandwidth reduced to 3.4 kHz)
– Accepts/outputs uncompressed audio in 8-bit PCM A/µ law or 16-bit linear format
– Uncompressed/compressed audio switchable between different interface combinations (IOM/Serial Audio Interface, IOM/Host, Host/Host)
– Inband controlled H.221/H.223 oriented audio protocol, e.g. for direct serial connection to videocodec (VCP of 8×8 Inc., formerly IIT Inc.) as well as host based solutions
– Stable reaction on interrupt handshake timing violations of e.g. a slow host (Windows® PC)

System On-chip Functions

– Two universal serial HDLC/transparent data controllers
– IOM-2 monitor and C/I channels
– Generation of programmable system clock output
– Three programmable timers
– Programmable on-chip PLL for internal clock generation from ISDN low frequency (7.68 MHz) clock

Interfaces

– 4-line IOM-2/PCM interface
– 5-line serial audio interface, e.g. for connection to videocodec/H.221/223 processor
– Parallel 8-bit Host interface
– 4-line general purpose interface
– External memory interface to external SRAM with programmable waitstates (0 to 15), for development purposes only.

Control

– Programmable via parallel host interface
– Operating parameters and mode settings via a register bank
– Access to audio channels and HDLC/serial transparent data controllers from DSP or an external host
– Interface to external software via a full-duplex 256-byte on-chip mailbox
– H.221/H.223 oriented inband configuration/mode switching

General

– Supply voltage: 3.0 - 3.6 V
– Additional 4.5 to 5.5 V supply for connection to 5-V systems without external components
– Ambient temperature range 0 °C to + 70 °C
– P-TQFP-100 package