MEC1-105-02-S-D-A

GENERAL DESCRIPTION

The MEC140X/1X is a family of keyboard and embedded controller designs customized for notebooks and tablet platforms. The MEC140X/1X family is a highly-configurable, mixed signal, advanced I/O controller architecture. Every device in the family incorporates a 32-bit MIPS32 M14K Microcontroller core with a closely-coupled SRAM for code and data. A secure boot-loader is used to download the custom firmware image from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior.

Common Features

• 3.3V Operation
• ACPI 3.0 Compliant
• PC2001 compliant
• VTR (standby) and VBAT Power Planes
- Low Standby Current in Sleep Mode
• Connected Standby Support
• 32kHz Clock Source
- Internal 32kHz Oscillator
- External 32kHz Clock Source
- 32kHz Crystal (XTAL) Supported
- Single-Ended 32kHz Clock Source
• LPC Host Interface
- LPC Specification 1.1 Compatible
- LPC I/O and Memory Cycles Decoded
- Supports optional signals: CLKRUN#, LPCPD#, SERIRQ, SMI#, EC_SCI# (ACPI PME Event)
- Supports 19.2 MHz to 33 MHz nominal bus clock speeds
• Configuration Register Set
- Compatible with ISA Plug-and-Play Standard
- EC-Programmable Base Address
• 8042 Emulated Keyboard Controller
- 8042 Style Host Interface
- Port 92 Legacy A20M Support
- Fast GATEA20 & Fast CPU_RESET
• System to EC Message Interface
- One Embedded Memory Interface
- Host Serial or Parallel IRQ Source
- Provides Two Windows to On-Chip SRAM for Host Access
- Two Register Mailbox Command Interface
- Mailbox Registers Interface
- Thirty-two 8-Bit Scratch Registers
- Two Register Mailbox Command Interface
- Two Register SMI Source Interface
- Five ACPI Embedded Controller Interfaces
- Four EC Interfaces
- One Power Management Interface
• MIPS32® M14K™ Microcontroller Core
- microMIPS-Compatible Instruction Set
- High-performance Multiply/Divide Unit
- Programmable clock frequencies: 48MHz, 12MHz, 3MHz, and 1MHz
- Sleep mode
- 2-wire Debug Interface (ICSP)
- 6 Breakpoints (4-instruction; 2-data)
- Enhanced to Support Debug in Heavy and Deep Sleep States
• Trace FIFO Debug Port (TFDP)
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