PSB7280FV2.1

Introduction

Overview
The PSB 7280 Joint Audio Decoder Encoder is a device which implements voice compression algorithms using the Low-Delay Code Excited Linear Prediction (LD- CELP) standard as defined in the ITU-T G.728 Recommendation, and for 7-kHz voice using the Sub-Band Coded Adaptive Differential PCM (SBC-ADPCM) coding according to the G.722 Recommendation. In addition G.711 PCM audio coding is also supported.
Thus in the G.728 mode it compresses a digitized PCM (64 kbit/s) or linear (128 kbit/s) voice signal into a 16 kbit/s bit stream, and vice versa. The algorithm is implemented in 16-bit fixed point arithmetic and complies with the newest fixed point specification set forth by the ITU.

Feature List

Functions
– G.728 compression/decompression (16 kbit/s)
– G.722 compression/decompression for 7-kHz audio (64, 56, 48 kbit/s)
– G.711 compression/decompression (64 kbit/s)
– Digital sampling rate conversion (16 kHz - 8 kHz) for G.722 audio with 8-kHz Codec (bandwidth reduced to 3.4 kHz)
– Accepts/outputs uncompressed audio in 8-bit PCM A/µ law or 16-bit linear format
– Uncompressed/compressed audio switchable between different interface combinations (IOM/Serial Audio Interface, IOM/Host, Host/Host)
– Inband controlled H.221/H.223 oriented audio protocol, e.g. for direct serial connection to videocodec (VCP of 8 × 8 Inc., formerly IIT Inc.) as well as host based solutions
– Outband controlled audio protocol with optimized data rate
– Stable reaction on interrupt handshake timing violations of e.g. a slow host (Windows® PC)

System On-chip Functions

– Two universal serial HDLC/transparent data controllers
– IOM-2 monitor and C/I channels
– Generation of programmable system clock output
– Three programmable timers
– Programmable on-chip PLL for internal clock generation from ISDN low frequency (7.68 MHz) clock